Mr. Kaizad Mistry is a Corporate Vice President and Co- Director of the Logic Technology Development group at Intel Corporation. He earned his B.Tech. degree in Electrical Engineering from IIT Bombay in 1984 and M.S. in Electrical Engineering from the University of Southern California, Los Angeles in 1986.

After completing his masters in electrical engineering in 1986, Mr. Mistry joined the semiconductor development arm of Digital Equipment Corp. At Digital Equipment Corp., he participated in the development of many generations of chip making technology, from 2um to 0.25um. In 1998, he joined Intel Corp in the Logic Technology development group and was appointed as Vice President in 2007
and Corporate Vice President in 2017.

Mr. Mistry is widely recognized as one of the world’ s leading expert s in scaling microelectronic chips to ever-smaller transistor dimensions, advancing Moore’s Law. In the late 1980’s and 1990’s, while at Digital Equipment Corp., he published extensively on the reliability of MOS transistors, including several papers that have become classics in the field. After joining Intel Corp in 1998, he led the development and introduction of manufacturing of many technology innovations, including the first-ever implementation of strained silicon, the world’s first implementation of high-k metal gate transistors and the first implementation of FinFET transistors. He currently co-manages the Logic Technology Development Group at Intel, overseeing the research and development of future semiconductor technologies, involving thousands of engineers and over 1500 Ph.D.s.

Mr. Mistry has been the co-recipient of a number of awards, including the 2015 SEMI Award for the implementation of bulk CMOS FinFET production; the 2012 SEMI Award for the first development, integration and introduction of a successful high-k dielectric and metal electrode gate stack for CMOS IC production; the 2011 TIME Magazine citation of Intel’s 22nm technology as one of the “best inventions of the year”; the 2008 SEMI Award for process integration of strain-enhanced mobility techniques for CMOS transistors; the 2007 TIME Magazine citation of Intel’s 45nm technology for one of the “best inventions of the year”. He has also received several best paper awards at various conferences. In 2010, he was elected Fellow of IEEE, one of the highest professional honors for electrical engineers, “for contributions to high performance complementary metal-oxide semiconductor technology and reliability.”